Xilinx XC9572 CPLD based Clock Divider generates a desirable clock by adjusting the DIP switches on the board.The output clock signal, since generated from a CPLD,i.e. completely digital circuit is almost jitter-free. This is suitable for the next circuit i.e. the PRBS Generator itself. To change the frequency of the randomness of the generated signal we just have to change the clock being generated by this circuit.

Xilinx XC2C64A CPLD based 8-bit PRBS Generator is the actual PRBS generator circuit. This particular CPLD is configured to generate a 8-bit random signal. It can be configured to generate a wider signal, like say 16-bit PRBS signal by just changing the VHDL code. However if an analog signal is needed then we will have to feed this signal to a DAC.

8-bit R-2R DAC to convert digital PRBS signal to analog voltage as viewed in the oscilloscope.

Xilinx XC9572 CPLD based Clock Divider generates a desirable clock by adjusting the DIP switches on the board.The output clock signal, since generated from a CPLD,i.e. completely digital circuit is almost jitter-free. This is suitable for the next circuit i.e. the PRBS Generator itself. To change the frequency of the randomness of the generated signal we just have to change the clock being generated by this circuit.

Xilinx XC2C64A CPLD based 8-bit PRBS Generator is the actual PRBS generator circuit. This particular CPLD is configured to generate a 8-bit random signal. It can be configured to generate a wider signal, like say 16-bit PRBS signal by just changing the VHDL code. However if an analog signal is needed then we will have to feed this signal to a DAC.

8-bit R-2R DAC to convert digital PRBS signal to analog voltage as viewed in the oscilloscope.

VHDL Code of D-FlipFlop

VHDL Code for D-Flipflop

VHDL Code:
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_ARITH.ALL;
  4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5.  
  6.  
  7. entity dff is
  8. Port ( CLK : in std_logic;
  9. RSTn : in std_logic;
  10. D : in std_logic;
  11. Q : out std_logic);
  12. end dff;
  13.  
  14.  
  15. architecture Behavioral of dff is
  16. begin
  17. process(CLK)
  18. begin
  19. if CLK'event and CLK='1' then
  20. if RSTn='1' then
  21. Q <= '1';
  22. else
  23. Q <= D;
  24. end if;
  25. end if;
  26. end process;
  27. end Behavioral;

VHDL code for LFSR

VHDL Code for PRBS Generator using LFSR

VHDL Code:
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4.  
  5. entity lfsr is
  6. Port ( CLK : in STD_LOGIC;
  7. RSTn : in STD_LOGIC;
  8. data_out : out STD_LOGIC_VECTOR (7 downto 0));
  9. end lfsr;
  10.  
  11. architecture Behavioral of lfsr is
  12.  
  13. component dff
  14. Port ( CLK : in std_logic;
  15. RSTn : in std_logic;
  16. D : in std_logic;
  17. Q : out std_logic);
  18. end component;
  19.  
  20. signal data_reg : std_logic_vector(7 downto 0);
  21. signal tap_data : std_logic;
  22.  
  23. begin
  24. process(CLK)
  25. begin
  26. tap_data <= (data_reg(1) xor data_reg(2)) xor (data_reg(4) xor
  27. data_reg(7));
  28. end process;
  29.  
  30. stage0: dff
  31. port map(CLK, RSTn, tap_data, data_reg(0));
  32.  
  33. g0:for i in 0 to 6 generate
  34.  
  35. stageN: dff
  36. port map(CLK, RSTn, data_reg(i), data_reg(i+1));
  37. end generate;
  38. data_out <= data_reg after 3 ns;
  39. end Behavioral;

VHDL Test-Bench Code for Simulating PRBS Generator using LFSR

VHDL Code:
  1. LIBRARY ieee;
  2. USE ieee.std_logic_1164.ALL;
  3.  
  4. ENTITY testprbs IS
  5. END testprbs;
  6.  
  7. ARCHITECTURE behavior OF testprbs IS
  8. -- Component Declaration for the Unit Under Test (UUT)
  9. COMPONENT lfsr
  10. PORT(
  11. CLK : IN std_logic;
  12. RSTn : IN std_logic;
  13. data_out : OUT std_logic_vector(7 downto 0)
  14. );
  15. END COMPONENT;
  16. signal CLK : std_logic := '0';
  17. signal RSTn : std_logic := '0';
  18. signal data_out : std_logic_vector(7 downto 0);
  19. -- Clock period definitions
  20. constant CLK_period : time := 10 ns;
  21.  
  22. BEGIN
  23. -- Instantiate the Unit Under Test (UUT)
  24. uut: lfsr PORT MAP (
  25. CLK => CLK,
  26. RSTn => RSTn,
  27. data_out => data_out
  28. );
  29. CLK_process :process
  30.  
  31. begin
  32. CLK <= '0';
  33. wait for CLK_period/2;
  34. CLK <= '1';
  35. wait for CLK_period/2;
  36. end process;
  37.  
  38. -- Stimulus process
  39. stim_proc: process
  40. begin
  41. wait for 10 ns;
  42. wait for CLK_period*1;
  43. RSTn <= '1';
  44. wait for CLK_period*1;
  45. RSTn <= '0';
  46. wait;
  47. end process;
  48.  
  49. END;

VHDL Code for Clock Divider

VHDL Code for Clock Divider

VHDL Code:
  1. --Programmable Clock Diveder Circuit
  2. --Engineer: Debashish Mohapatra, 9938040894
  3. --Input Clock Frequency 4MHz, 11.059 Mhz, 16 MHz, 24 MHz
  4.  
  5. --An 8 bit selector push button array to set the divide by factor
  6. --Square of the factor_select input to set the prescaler
  7. --e.g. is select switch inpput reads 3, then-- prescaler is set to square of 3 i.e. 9
  8.  
  9. -------------------------------------------
  10. library IEEE;
  11. USE IEEE.STD_LOGIC_1164.ALL;
  12. USE IEEE.NUMERIC_STD.ALL;
  13.  
  14. entity clock_divider is
  15. Port ( clk_in : in STD_LOGIC;
  16. rst : in STD_LOGIC;
  17. factor_select : in STD_LOGIC_VECTOR (7 downto 0);
  18. sw : in std_logic;
  19.  
  20. LED : out std_logic;
  21. clk_out : out STD_LOGIC);
  22. end clock_divider;
  23.  
  24. architecture Behavioral of clock_divider is
  25.  
  26. signal factor_final : std_logic_vector (15 downto 0);
  27. -- signal factor_usgn : unsigned (7 downto 0);
  28. -- signal factor_int : integer :=0;
  29. signal prescaler : integer :=0;
  30.  
  31. signal counter : integer := 0;
  32. signal temp_clk_out : std_logic;
  33.  
  34. -- signal count_out : integer :=0;
  35. signal led_state : std_logic := '0';
  36.  
  37. begin
  38. factor_final <= factor_select & factor_select;
  39. -- factor_usgn <= unsigned (factor_select);
  40. -- --Std logic vector to unsigned conversion
  41. -- factor_int <= to_integer(factor_usgn);
  42. -- --Unsigned to Integer conversion
  43. -- -- Or factor_int <= to_integer(unsigned(factor_select));
  44. -- prescaler <= factor_int;
  45. -- -- set prescler to the integer equivalent of the read value from buttons
  46.  
  47. frequency_divider:process(rst, clk_in, sw) begin
  48. if (rst = '0') then
  49. temp_clk_out <= '0';
  50. counter <= 0;
  51. elsif rising_edge(clk_in) then
  52. if (sw = '0') then
  53. prescaler <= to_integer(unsigned(factor_select));
  54. elsif (sw ='1') then
  55. prescaler <= to_integer(unsigned(factor_final));
  56. else
  57. prescaler <= 0;
  58. end if;
  59.  
  60. if (counter = prescaler) then
  61. temp_clk_out <= not(temp_clk_out);
  62. counter <= 0;
  63. led_state <= not (led_state);
  64. else
  65. counter <= counter + 1;
  66. end if;
  67. end if;
  68. end process;
  69. clk_out <= temp_clk_out;
  70.  
  71. -- led_blinking : process (temp_clk_out) begin
  72. -- if rising_edge(temp_clk_out) then
  73. -- if (count_out = 256) then
  74. -- count_out <= 0;
  75. -- led_state <= not (led_state);
  76. -- else
  77. -- count_out <= count_out +1;
  78. -- end if;
  79. -- end if;
  80. -- end process;
  81. led <= led_state;
  82. end Behavioral;

Expt. Setup

Results