The FPGA uses a 624-point look-up table stored in its RAM, which contains the 10-bit values of the sine wave. These values are written to the 10-bit output ports. A 10-bit R-2R DAC connected to theses ports convert these digital values to an analog voltage which lies between 0 volt to 3.3 volt.

VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.NUMERIC_STD.ALL; --try to use this library as much as possible.
  5.  
  6. entity Sine_Gen_10bit is
  7. port (clk :in std_logic;
  8.  
  9. sine_out_1 : out std_logic_vector (9 downto 0);
  10. sine_out_2 : out std_logic_vector (9 downto 0);
  11. sine_out_3 : out std_logic_vector (9 downto 0)
  12. );
  13. end Sine_Gen_10bit;
  14.  
  15. architecture Behavioral of Sine_Gen_10bit is
  16. signal i : integer range 0 to 623:=0;
  17. signal j : integer range 0 to 623:=207;
  18. signal k : integer range 0 to 623:=415;
  19. type memory_type is array (0 to 623) of integer range 0 to 1023;
  20. --ROM for storing the sine values generated by MATLAB.
  21.  
  22. signal sine : memory_type :=(512,517,522,527,532,537,542,548,553,558,563,568,573,578,583,588,594,599,604,609,614,619,624,629,634,639,644,649,654,659,664,669,673,678,683,688,693,698,702,707,712,717,721,726,731,735,740,745,749,754,758,763,767,772,776,781,785,789,794,798,802,806,810,815,819,823,827,831,835,839,843,847,851,855,858,862,866,870,873,877,880,884,887,891,894,898,901,904,908,911,914,917,920,923,927,930,932,935,938,941,944,947,949,952,954,957,960,962,964,967,969,971,974,976,978,980,982,984,986,988,990,992,993,995,997,998,1000,1001,1003,1004,1006,1007,1008,1009,1011,1012,1013,1014,1015,1016,1016,1017,1018,1019,1019,1020,1020,1021,1021,1022,1022,1022,1023,1023,1023,1023,1023,1023,1023,1023,1023,1022,1022,1022,1021,1021,1020,1020,1019,1019,1018,1017,1016,1016,1015,1014,1013,1012,1011,1009,1008,1007,1006,1004,1003,1001,1000,998,997,995,993,992,990,988,986,984,982,980,978,976,974,971,969,967,964,962,960,957,954,952,949,947,944,941,938,935,932,930,927,923,920,917,914,911,908,904,901,898,894,891,887,884,880,877,873,870,866,862,858,855,851,847,843,839,835,831,827,823,819,815,810,806,802,798,794,789,785,781,776,772,767,763,758,754,749,745,740,735,731,726,721,717,712,707,702,698,693,688,683,678,673,669,664,659,654,649,644,639,634,629,624,619,614,609,604,599,594,588,583,578,573,568,563,558,553,548,542,537,532,527,522,517,512,506,501,496,491,486,481,475,470,465,460,455,450,445,440,435,429,424,419,414,409,404,399,394,389,384,379,374,369,364,359,354,350,345,340,335,330,325,321,316,311,306,302,297,292,288,283,278,274,269,265,260,256,251,247,242,238,234,229,225,221,217,213,208,204,200,196,192,188,184,180,176,172,168,165,161,157,153,150,146,143,139,136,132,129,125,122,119,115,112,109,106,103,100,96,93,91,88,85,82,79,76,74,71,69,66,63,61,59,56,54,52,49,47,45,43,41,39,37,35,33,31,30,28,26,25,23,22,20,19,17,16,15,14,12,11,10,9,8,7,7,6,5,4,4,3,3,2,2,1,1,1,0,0,0,0,0,0,0,0,0,1,1,1,2,2,3,3,4,4,5,6,7,7,8,9,10,11,12,14,15,16,17,19,20,22,23,25,26,28,30,31,33,35,37,39,41,43,45,47,49,52,54,56,59,61,63,66,69,71,74,76,79,82,85,88,91,93,96,100,103,106,109,112,115,119,122,125,129,132,136,139,143,146,150,153,157,161,165,168,172,176,180,184,188,192,196,200,204,208,213,217,221,225,229,234,238,242,247,251,256,260,265,269,274,278,283,288,292,297,302,306,311,316,321,325,330,335,340,345,350,354,359,364,369,374,379,384,389,394,399,404,409,414,419,424,429,435,440,445,450,455,460,465,470,475,481,486,491,496,501,506);
  23.  
  24. begin
  25.  
  26. process(clk)
  27. begin
  28. --to check the rising edge of the clock signal
  29. if(rising_edge(clk)) then
  30.  
  31. --use ieee.numeric_std.all;
  32. --...
  33. --my_slv <= std_logic_vector(to_unsigned(my_int, my_slv'length));
  34.  
  35. sine_out_1 <= std_logic_vector(to_unsigned(sine(i),sine_out_1'length));
  36. sine_out_2 <= std_logic_vector(to_unsigned(sine(j),sine_out_2'length));
  37. sine_out_3 <= std_logic_vector(to_unsigned(sine(k),sine_out_3'length));
  38. i <= i+ 1;
  39. j <= j+ 1;
  40. k <= k+ 1;
  41. if(i = 623) then
  42. i <= 0;
  43. end if;
  44. if(j = 623) then
  45. j <= 0;
  46. end if;
  47. if(k = 623) then
  48. k <= 0;
  49. end if;
  50. end if;
  51. end process;
  52.  
  53. end Behavioral;
  54.