Tanner tools Tutorial

 

Requirements:

  • Tanner Tools Installed and licenced properly
  • The proper library file, extract rule set file and a pre-designed database file. You can find them in your documents folder with the name “Layout File”.

If you don’t have them then download them as a Zip file or as an WinRAR archieve or Individual files as nmos.tdb, NMOS.tdo, mhp_n05.ext, mhp_n05.tdb, BSIM_50.md.

  • A little knowledge about the layout of any digital circuit, or a CMOS designs (Stick diagram will also help).

Procedure (A step by step Demonstration):

  1. Launch Tanner Tools L-Edit, by double clicking the icon on desktop or from your program files list in the start menu (i.e. start menu > Program files >Tanner EDA >Tanner Tools V13.0 >L-edit.

 

 

  1. Then open the nmos.tdb file, from the “layout file” folder in Documents. We will use this design to create our own cell i.e. nmos, pmos, inverter, nand & nor gates etc. We will not have to configure every design parameters of our own.

 

 

 

 

 

 

  1. Now create your own Cell in which you will design your own circuits/transistors.

 


 

 

  1. Give your cell a name and any additional details.

 

 

  1. Now adjust the grid, such as The Bigger Dots (prominent black ones) and the (Smaller Dots).To do this you need to first click in the drawing area, and then, zoom in or out of the grid by holding down Ctrl and Scrolling the Mouse Wheel.
  2. Now we are ready to draw our design.
     

    Tanner tools Tutorial

     

    Requirements:

    • Tanner Tools Installed and licenced properly
    • The proper library file, extract rule set file and a pre-designed database file. You can find them in your documents folder with the name “Layout File”.

    If you don’t have them then download them as a Zip file or as an WinRAR archieve or Individual files as nmos.tdb, NMOS.tdo, mhp_n05.ext, mhp_n05.tdb, BSIM_50.md.

    • A little knowledge about the layout of any digital circuit, or a CMOS designs (Stick diagram will also help).

    Procedure (A step by step Demonstration):

    1. Launch Tanner Tools L-Edit, by double clicking the icon on desktop or from your program files list in the start menu (i.e. start menu > Program files >Tanner EDA >Tanner Tools V13.0 >L-edit.

     

     

    1. Then open the nmos.tdb file, from the “layout file” folder in Documents. We will use this design to create our own cell i.e. nmos, pmos, inverter, nand & nor gates etc. We will not have to configure every design parameters of our own.

     

     

     

     

     

     

    1. Now create your own Cell in which you will design your own circuits/transistors.

     


     

     

    1. Give your cell a name and any additional details.

     

     

    1. Now adjust the grid, such as The Bigger Dots (prominent black ones) and the (Smaller Dots).To do this you need to first click in the drawing area, and then, zoom in or out of the grid by holding down Ctrl and Scrolling the Mouse Wheel.
    2. Now we are ready to draw our design.

    Drawing the Layers

1)      First click on the active contact (Black coloured) on the left side of the drawing area.

 

2)      Then select the “draw rectangle tool” to start drawing the layers.

 

 

3)      Now draw a Active Contact Layer of (2x2) lambda.

 

 

 

4)      Now in a very similar way draw these layers

 

Metal1 (4x4) lambda

 

Active (6x6) lambda (although minimum Allowable width of active is 5, however to make our drawing easy and uniform make it 6x6 lambda).

 

Tip:

While drawing the layers to adjust the size, i.e decrease or increase the area, you need to move the edge of a layer. To do that, first select the arrow tool, which is given in the top toolbar, just beside the “drawing box tool”. Then select the layer you want to modify, by doing a “Left Mouse Click” on the desired layer. Then  hold down “Alt” and left click (with mouse of course) on the edge you want to move and While holding down Mouse left button drag the edge outward or inward to increase or decrease the area.

 

 

 

Rearranging the layers

 

5)      Now arrange the above three layers on top of another. To move the layers around, hold down the “Alt” key and drag the layer with holding down “left mouse button”. This technique may seem a little tricky at first for newbies, but you will eventually get it with patience.


 

6)      The above arrangement of the three layers will serve as one of the drain/source/body terminal. To make all the three terminals either repeat the above drawing steps and make such two more drawings, or you can just copy paste the whole thing to duplicate the drawing.I would recommend to draw similar two layers by hand wile you are practising this initially to improve your familiarity with the drawing, but once you know it you can opt for the time saving copy-paste way.

 

To duplicate a design, select the “arrow tool”, draw a selection box around the drawing, by “left click”, hold left click and Drag the mouse around the drawing, then release it.

 

 

 

 

 

 

Once you release the mouse button you can see the edges highlighted. Now press “Ctrl+C” to copy and press “Ctrl+V” to paste, the good old windows copy paste method.

 

 

After you Paste it , you should move the Drawings to their proper positions, so as you can later on make them as the three terminals, i.e. Source/Drain/Body.

 

 

Drawing The Channel and Gate

 

7)      The next step is to make the layer which will serve as channel. For that, join the first two drawings, by an active with minimum width of 5 lambda.

 

 

8)      Then let us make the gate, by crossing the channel region (created in the previous step) with the poly. Select the poly from the Left side toolbox, i.e. the red one, and draw a layer of minimum 2 lambda in width, intersecting the channel.

 

Drawing the substrates/Body.

 

9)      Now that, our source/drain/gate/and body terminals are prepared (partially of course), let us draw the substrate.

Note: In a N-Mos, the substrate is made of P-type, where as the active regions such as the Drain/Source and the Channel are of N++ Type.

So to create a N++ region, we have to cross the active layer, with N-select Layer.

Let us Do that, by picking up the N-select layer from the left and drawing a Layer which includes the active regions.

 

 

10)   Then to get the body/Substrate terminal (which is of the type P+), cross the Body Active with P-select.

 

The metal and Interconnections

11)   Now we got all the four terminals of our N-Mos, we need to make the actual metal contact, to which we will give the supplies i.e Vdd, gnd or so on.

For that, we need to draw Metal1 layer with minimum width of 4 lambda as shown here.

 

 

 

 

12)   Then we need to join the metal1 layers of our previously created terminals to that of the vdd and gnd as shown in the following steps.

 

 

 

 

 

 

 

Naming the Terminals

13)   After completing the drawing of all the layers and interconnections, we need to name the terminals, which we will use in our analysis later on. For this purpose, select the Name tool (or Drawing Ports Tool) from the upper toolbar, as indicated below.

 

 

14)   Then click on the layers as shown below, and name them.

 

 

 

15)   You need to select the layer to be named, very carefully, and then give the port a name.

 

 

 

16)   Similarly name the Gnd and gate as shown in the following figures.

 

 

 

The Design Rule Check (DRC)

 

17)   Now that our drawing and naming the ports is complete, we need to check the design for any design error. There is an inbuilt tool, known as The DRC (Design rule check).The button is shown below. Find it in the toolbar, and click on it.

 

 

 

 

 

 

 


If you find any error here, then rectify them, run the DRC again, till you get the error free design, and then only proceed forward.

Extracting the SPICE Netlist

 

18)   Now that our design is complete, we need to verify its functionality, by simulating our design. For this purpose, we will use a spice tool, i.e. Tanner Spice or T-Spice, But we need to first get the definition of our design element/ckt (as the case may be, but here it is our N-MOS) into spice. This is known as extraction. Where the tool will extract (the Net-list ) all the node names, and their interconnection information into a spice code.

To do this, find the setup extract button first as shown below and set up the parameters as shown.

 

 

 

 

 

 

 


 

19)   Now we are ready to extract the net-list into spice. Find the Extract button on the upper toolbar as shown.

 

20)   Then click the extract button to begin the extraction process. It may happen, that the tool will ask about unknown capacitance and all, just hit the Ignore all button.

 

 

 

 

Simulation in T-Spice

 

21)   Then upon completion of the extract, open the layout_file folder, to find the extracted spice code.

 

22)   Double click that spice file to, open in T-spice, the tool for analysis and simulation, by Tanner EDA.

 

 

 

23)   Here you can see the extracted code for your design. Now add your own codes. In this example the codes are added to perform a DC analysis of the N-MOS.

 

.model nmos nmos level=1

 

v1 vdd gnd dc 5

vg gate gnd dc 5

 

.dc v1 0 5 .1 vg 0 5 1

.print dc i(m1,vdd)

 

24)   Now that we have finished editing the spice file, we are ready to run the simulation. Find the simulation on the upper toolbar and click it.

The tool will simulate the circuit, and will show the interpreted result in a graphical from, as we had included a Print Command in the spice code.

For DC Analysis of NMOS, the current at VDD is printed as below.

 

 

 

This completes our little introduction to tanner tools to draw a layout, extract the net-list from the layout and simulate it and interpret the result.

 

Article written by Debashish Mohapatra, Lecturer, PIET, Rourkela (http://www.debashish.info/)