VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7. entity ha is
  8. Port ( a,b : in STD_LOGIC;
  9. s,c : out STD_LOGIC);
  10. end ha;
  11.  
  12. architecture ha_dataflow of ha is
  13.  
  14. begin
  15.  
  16. s <= a xor b;
  17. c <= a and b;
  18.  
  19. end ha_dataflow;
  20.