VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7.  
  8. entity fa is
  9. Port ( a,b,cin : in STD_LOGIC;
  10. s,cout : out STD_LOGIC);
  11. end fa;
  12.  
  13. architecture fa_dataflow of fa is
  14.  
  15. begin
  16.  
  17. s<= a xor b xor cin;
  18. cout<= (a and b) or(b and cin) or (cin and a);
  19. end fa_dataflow;
  20.