VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7. entity fa_str is
  8. Port ( a,b,cin : in STD_LOGIC;
  9. s,cout : out STD_LOGIC);
  10. end fa_str;
  11.  
  12. architecture fa_struct of fa_str is
  13.  
  14. component ha
  15. port (a,b:in std_logic;
  16. s,c: out std_logic);
  17. end component;
  18.  
  19. component or21
  20. port (a,b: in std_logic;
  21. y: out std_logic);
  22. end component;
  23.  
  24. signal t1,t2,t3 : std_logic;
  25.  
  26. begin
  27. h1: ha port map (a,b,t2,t1);
  28. h2: ha port map (t2,cin,s,t3);
  29. h3: or21 port map (t1,t3,cout);
  30. end fa_struct;
  31.