VHDL Code:
  1.  
  2.  
  3. library IEEE;
  4. use IEEE.STD_LOGIC_1164.ALL;
  5. use IEEE.STD_LOGIC_ARITH.ALL;
  6. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  7.  
  8.  
  9.  
  10. entity adder_4bit_rc is
  11. Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
  12. s : out STD_LOGIC_VECTOR (3 downto 0);
  13. cout : out STD_LOGIC);
  14. end adder_4bit_rc;
  15.  
  16. architecture struct of adder_4bit_rc is
  17. signal c: std_logic_vector(4 downto 0);
  18. component fa is
  19. Port ( a,b,cin : in STD_LOGIC;
  20. s,cout : out STD_LOGIC);
  21. end component;
  22. begin
  23. c(0)<='0';
  24. F1: fa port map (a(0),b(0),c(0),s(0),c(1));
  25. F2: fa port map (a(1),b(1),c(1),s(1),c(2));
  26. F3: fa port map (a(2),b(2),c(2),s(2),c(3));
  27. F4: fa port map (a(3),b(3),c(3),s(3),c(4));
  28. cout<=c(4);
  29. end struct;
  30.  
  31.  
  32.  
  33.