VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7.  
  8. entity mux2x1 is
  9. Port ( a,b,s : in STD_LOGIC;
  10. y : out STD_LOGIC);
  11. end mux2x1;
  12.  
  13. architecture mux2x1_dataflow of mux2x1 is
  14.  
  15. begin
  16. y<= (not(s) and a) or(s and b);
  17.  
  18. end mux2x1_dataflow;
  19.  
  20.