VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7. entity mux4x1_struct is
  8. Port ( a,b,c,d,s0,s1 : in STD_LOGIC;
  9. y : out STD_LOGIC);
  10. end mux4x1_struct;
  11.  
  12. architecture struct_2mux of mux4x1_struct is
  13.  
  14. component mux2x1 is
  15. Port ( a,b,s : in STD_LOGIC;
  16. y : out STD_LOGIC);
  17. end component;
  18. signal t1,t2: std_logic;
  19. begin
  20. m1:mux2x1 port map (a,b,s0,t1);
  21. m2:mux2x1 port map (c,d,s0,t2);
  22. m3:mux2x1 port map (t1,t2,s1,y);
  23.  
  24. end struct_2mux;
  25.