4:1 Mux Dataflow Modelling 

VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7. entity mux4x1 is
  8. Port ( a,b,c,d,s0,s1 : in  STD_LOGIC;
  9. y : out  STD_LOGIC);
  10. end mux4x1;
  11.  
  12. architecture mux4x1_dataflow of mux4x1 is
  13.  
  14. begin
  15.  
  16. y<= ((not s0) and (not s1) and a) or ((not s1) and s0 and b) or (s1 and (not s0) and c) or (s0 and s1 and d);
  17.  
  18. end mux4x1_dataflow;
  19.  
  20.