VHDL Code:
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity mux4x1 is
Port ( a,b,c,d,s0,s1 : in  STD_LOGIC;
y : out  STD_LOGIC);
end mux4x1;
 
architecture mux4x1_dataflow of mux4x1 is
 
begin
 
y<= ((not s0) and (not s1) and a) or ((not s1) and s0 and b) or (s1 and (not s0) and c) or (s0 and s1 and d);
 
end mux4x1_dataflow;