VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7. entity mux4x1_when_else is
  8. Port ( a,b,c,d: in STD_LOGIC;
  9. s: in std_logic_vector (1 downto 0);
  10. y : out STD_LOGIC);
  11. end mux4x1_when_else;
  12.  
  13. architecture mux4x1_when_else_modeling of mux4x1_when_else is
  14.  
  15. begin
  16. y <= a when s="00" else
  17. b when s="01" else
  18. c when s="10" else
  19. d;
  20.  
  21. end mux4x1_when_else_modeling;
  22.  
  23.