VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7. entity mux4x1_case is
  8. Port ( a,b,c,d : in STD_LOGIC;
  9. s : in STD_LOGIC_VECTOR (1 downto 0);
  10. y : out STD_LOGIC);
  11. end mux4x1_case;
  12.  
  13. architecture mux_case of mux4x1_case is
  14.  
  15. begin
  16. process(s,a,b,c,d)
  17. begin
  18. case s is
  19. when "00" => y <= a;
  20. when "01" => y <= b;
  21. when "10" => y <= c;
  22. when others => y <= d;
  23. end case;
  24. end process;
  25. end mux_case;
  26.  
  27.