VHDL Code:
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity mux4x1_if_else is
Port ( a,b,c,d : in  STD_LOGIC;
s : in  STD_LOGIC_VECTOR (1 downto 0);
y : out  STD_LOGIC);
end mux4x1_if_else;
 
architecture Behavioral_if_else of mux4x1_if_else is
 
begin
process (s,a,b,c,d)
begin
if (s="00") then y <=a ; elsif (s="01") then y<=b ; elsif (s="10") then y<=c; else y<=d;
end if;
end process;
end Behavioral_if_else;