VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7. entity mux4x1_if_else is
  8. Port ( a,b,c,d : in STD_LOGIC;
  9. s : in STD_LOGIC_VECTOR (1 downto 0);
  10. y : out STD_LOGIC);
  11. end mux4x1_if_else;
  12.  
  13. architecture Behavioral_if_else of mux4x1_if_else is
  14.  
  15. begin
  16. process (s,a,b,c,d)
  17. begin
  18. if (s="00") then y <=a ; elsif (s="01") then y<=b ; elsif (s="10") then y<=c; else y<=d;
  19. end if;
  20. end process;
  21. end Behavioral_if_else;
  22.  
  23.