VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7. entity mux_4x1_mixed is
  8. Port ( a,b,c,d,s0,s1 : in STD_LOGIC;
  9. y : out STD_LOGIC);
  10. end mux_4x1_mixed;
  11.  
  12. architecture mixed of mux_4x1_mixed is
  13. component or4x1 port (p,q,r,s: in std_logic;
  14. t: out std_logic);
  15. end component;
  16. signal s0bar,s1bar,t1,t2,t3,t4:std_logic;
  17. begin
  18. process (s0,s1)
  19. begin
  20. s0bar<=not(s0);
  21. s1bar<=not(s1);
  22. end process;
  23. t1<=s0bar and s1bar and a ;
  24. t2<=s1bar and s0 and b ;
  25. t3<=s1 and s0bar and c ;
  26. t4<=s0 and s1 and d ;
  27. G1: or4x1 port map (t1,t2,t3,t4,y);
  28. end mixed;
  29.  
  30.