VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7. entity bcd_to_ssd is
  8. Port ( b : in STD_LOGIC_VECTOR (3 downto 0);
  9. y : out STD_LOGIC_VECTOR (6 downto 0));
  10. end bcd_to_ssd;
  11.  
  12. architecture Behavioral of bcd_to_ssd is
  13.  
  14. begin
  15. process(b)
  16. begin
  17. case b is
  18. when"0000"=>y<= "1111110";
  19. when"0001"=>y<= "0110000";
  20. when"0010"=>y<= "1101101";
  21. when"0011"=>y<= "1111001";
  22. when"0100"=>y<= "0110011";
  23. when"0101"=>y<= "1011011";
  24. when"0110"=>y<= "1011111";
  25. when"0111"=>y<="1110000";
  26. when"1000"=>y<= "1111111";
  27. when"1001"=>y<="1111011";
  28. when others=> null;
  29. end case;
  30. end process;
  31. end Behavioral;
  32.