VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7. entity add_to_ssd is
  8. Port ( a,b : in STD_LOGIC_VECTOR (1 downto 0);
  9. y : out STD_LOGIC_vector (6 downto 0));
  10. end add_to_ssd;
  11.  
  12. architecture Hybrid of add_to_ssd is
  13.  
  14. component fa
  15. Port ( a,b,cin : in STD_LOGIC;
  16. s,cout : out STD_LOGIC);
  17. end component;
  18.  
  19. signal r: std_logic_vector(2 downto 0);
  20. constant cin: std_logic :='0';
  21. signal c: std_logic;
  22.  
  23. begin
  24. a1: fa port map (a(0),b(0),cin,r(0),c);
  25. a2: fa port map (a(1),b(1),c,r(1),r(2));
  26.  
  27. y<= "1111110" when r="000" else
  28. "0110000" when r="001" else
  29. "1101101" when r="010" else
  30. "1111001" when r="011" else
  31. "0110011" when r="100" else
  32. "1011011" when r="101" else
  33. "1011111" when r="110" else
  34. "1110000" when r="111" ;
  35.  
  36.  
  37. end Hybrid;
  38.  
  39.