VHDL Code:
  1.  
  2.  
  3. library IEEE;
  4. use IEEE.STD_LOGIC_1164.ALL;
  5. use IEEE.STD_LOGIC_ARITH.ALL;
  6. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  7.  
  8. entity dec is
  9. Port ( a,b,en : in STD_LOGIC;
  10. z : out STD_LOGIC_vector( 3 downto 0));
  11. end dec;
  12.  
  13. architecture Behavioral of dec is
  14. signal abar,bbar:std_logic;
  15. begin
  16. z(0)<=not(abar and bbar and en);
  17. z(1)<=not(a and bbar and en);
  18. z(2)<=not(abar and b and en);
  19. z(3)<=not(a and b and en);
  20. abar<=not a;
  21. bbar<=not b;
  22. end Behavioral;
  23.  
  24.