VHDL Code:
  1.  
  2.  
  3. library IEEE;
  4. use IEEE.STD_LOGIC_1164.ALL;
  5. use IEEE.STD_LOGIC_ARITH.ALL;
  6. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  7.  
  8. entity decoder3x8 is
  9. Port ( i : in STD_LOGIC_VECTOR (2 downto 0);
  10. y : out STD_LOGIC_VECTOR (7 downto 0));
  11. end decoder3x8;
  12.  
  13. architecture Behavioral of decoder3x8 is
  14.  
  15. begin
  16.  
  17. process(i)
  18. begin
  19. case i is
  20. when "111" => y<="00000001";
  21. when "110" => y<="00000010";
  22. when "101" => y<="00000100";
  23. when "100" => y<="00001000";
  24. when "011" => y<="00010000";
  25. when "010" => y<="00100000";
  26. when "001" => y<="01000000";
  27.  
  28. when "000" => y<="10000000";
  29. when others => null;
  30. end case;
  31. end process;
  32. end Behavioral;
  33.  
  34.  
  35.