VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7. entity alu is
  8. Port ( a,b,s : in STD_LOGIC_VECTOR (1 downto 0);
  9. y : out STD_LOGIC_VECTOR (2 downto 0));
  10. end alu;
  11.  
  12. architecture dataflow of alu is
  13.  
  14.  
  15. begin
  16.  
  17. y<= (a + b) when s="00" else (a-b) when s="01" else (a and b) when s="10" else (a or b) when s="11";
  18.  
  19. end dataflow;
  20.