VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.STD_LOGIC_ARITH.ALL;
  5. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  6.  
  7. entity gray_to_binary is
  8. Port ( g : in STD_LOGIC_VECTOR (3 downto 0);
  9. b : out STD_LOGIC_VECTOR (3 downto 0));
  10. end gray_to_binary;
  11.  
  12. architecture dataflow of gray_to_binary is
  13.  
  14. begin
  15.  
  16. b(0)<= g(0) xor g(1) xor g(2) xor g(3);
  17. b(1)<= g(1) xor g(2) xor g(3);
  18. b(2)<= g(2) xor g(3);
  19. b(3)<= g(3);
  20.  
  21. end dataflow;
  22.