VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4.  
  5. entity Adder_8bit is
  6. Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
  7. b : in STD_LOGIC_VECTOR (7 downto 0);
  8. cin:in std_logic;
  9. s : out std_logic_vector(7 downto 0);
  10. cout : out STD_LOGIC);
  11. end Adder_8bit;
  12.  
  13. architecture Structural of Adder_8bit is
  14.  
  15. signal c: std_logic_vector(8 downto 0);
  16.  
  17. component FullAdder is
  18. Port ( a,b,cin : in STD_LOGIC;
  19. s,cout : out STD_LOGIC);
  20. end component;
  21.  
  22. begin
  23. c(0)<=cin;
  24. F1: FullAdder port map (a(0),b(0),c(0),s(0),c(1));
  25. F2: FullAdder port map (a(1),b(1),c(1),s(1),c(2));
  26. F3: FullAdder port map (a(2),b(2),c(2),s(2),c(3));
  27. F4: FullAdder port map (a(3),b(3),c(3),s(3),c(4));
  28. F5: FullAdder port map (a(4),b(4),c(4),s(4),c(5));
  29. F6: FullAdder port map (a(5),b(5),c(5),s(5),c(6));
  30. F7: FullAdder port map (a(6),b(6),c(6),s(6),c(7));
  31. F8: FullAdder port map (a(7),b(7),c(7),s(7),c(8));
  32. cout<=c(8);
  33.  
  34. end Structural;
  35.  
  36.  
  37. VHDL Test Bench for Full Adder:
  38.  
  39. LIBRARY ieee;
  40. USE ieee.std_logic_1164.ALL;
  41.  
  42. -- Uncomment the following library declaration if using
  43. -- arithmetic functions with Signed or Unsigned values
  44. --USE ieee.numeric_std.ALL;
  45.  
  46. ENTITY TestRippleCarryAdder IS
  47. END TestRippleCarryAdder;
  48.  
  49. ARCHITECTURE behavior OF TestRippleCarryAdder IS
  50.  
  51. -- Component Declaration for the Unit Under Test (UUT)
  52.  
  53. COMPONENT Adder_8bit
  54. PORT(
  55. a : IN std_logic_vector(7 downto 0);
  56. b : IN std_logic_vector(7 downto 0);
  57. cin : IN std_logic;
  58. s : OUT std_logic_vector(7 downto 0);
  59. cout : OUT std_logic
  60. );
  61. END COMPONENT;
  62.  
  63.  
  64. --Inputs
  65. signal a : std_logic_vector(7 downto 0) := (others => '0');
  66. signal b : std_logic_vector(7 downto 0) := (others => '0');
  67. signal cin : std_logic := '0';
  68.  
  69. --Outputs
  70. signal s : std_logic_vector(7 downto 0);
  71. signal cout : std_logic;
  72. -- No clocks detected in port list. Replace below with
  73. -- appropriate port name
  74.  
  75. constant clock_period : time := 10 ns;
  76.  
  77. BEGIN
  78.  
  79. -- Instantiate the Unit Under Test (UUT)
  80. uut: Adder_8bit PORT MAP (
  81. a => a,
  82. b => b,
  83. cin => cin,
  84. s => s,
  85. cout => cout
  86. );
  87.  
  88.  
  89. -- Stimulus process
  90. stim_proc: process
  91. begin
  92. -- hold reset state for 100 ns.
  93. wait for 10 ns;
  94. a <= "00000000";
  95. b <= "00000001";
  96. cin <= '0';
  97. wait for clock_period*1;
  98. a <= "00000001";
  99. b <= "00000001";
  100. cin <='0';
  101. wait for clock_period*1;
  102. a <= "00000000";
  103. b <= "00000001";
  104. cin <= '1';
  105. wait for clock_period*1;
  106. a <= "00000001";
  107. b <= "00000001";
  108. cin <= '1';
  109. wait for clock_period*1;
  110. a <= "11111111";
  111. b <= "11111111";
  112. cin <= '0';
  113. wait for clock_period*1;
  114. a <= "11111111";
  115. b <= "11111111";
  116. cin <= '1';
  117. wait for clock_period*1;
  118. a <= "00001010";
  119. b <= "01010101";
  120. cin <= '1';
  121. -- insert stimulus here
  122.  
  123. wait;
  124. end process;
  125.  
  126. END;
  127.  
  128.  
  129.