VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4. use IEEE.NUMERIC_STD.ALL;
  5.  
  6. entity FourBitMultiplier is
  7. Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
  8. B : in STD_LOGIC_VECTOR (3 downto 0);
  9. Result : out STD_LOGIC_VECTOR (7 downto 0));
  10. end FourBitMultiplier;
  11.  
  12. architecture Dataflow of FourBitMultiplier is
  13.  
  14. begin
  15.  
  16. Result <= std_logic_vector(unsigned(A) * unsigned(B));
  17.  
  18. end Dataflow;
  19.  
  20. VHDL Test Bench for 4-Bit Multiplier:
  21.  
  22. LIBRARY ieee;
  23. USE ieee.std_logic_1164.ALL;
  24.  
  25. ENTITY TestFourBitMultiplier IS
  26. END TestFourBitMultiplier;
  27.  
  28. ARCHITECTURE behavior OF TestFourBitMultiplier IS
  29.  
  30. -- Component Declaration for the Unit Under Test (UUT)
  31.  
  32. COMPONENT FourBitMultiplier
  33. PORT(
  34. A : IN std_logic_vector(3 downto 0);
  35. B : IN std_logic_vector(3 downto 0);
  36. Result : OUT std_logic_vector(7 downto 0)
  37. );
  38. END COMPONENT;
  39.  
  40.  
  41. --Inputs
  42. signal A : std_logic_vector(3 downto 0) := (others => '0');
  43. signal B : std_logic_vector(3 downto 0) := (others => '0');
  44.  
  45. --Outputs
  46. signal Result : std_logic_vector(7 downto 0);
  47. -- No clocks detected in port list. Replace below with
  48. -- appropriate port name
  49.  
  50. constant clock_period : time := 10 ns;
  51.  
  52. BEGIN
  53.  
  54. uut: FourBitMultiplier PORT MAP (
  55. A => A,
  56. B => B,
  57. Result => Result
  58. );
  59.  
  60. stim_proc: process
  61. begin
  62. -- hold reset state for 100 ns.
  63. wait for 100 ns;
  64.  
  65. A <= "0000";
  66. B <= "1010";
  67. wait for clock_period*10;
  68.  
  69. A <= "1111";
  70. B <= "1010";
  71. wait for clock_period*10;
  72.  
  73. A <= "1111";
  74. B <= "1111";
  75.  
  76. wait;
  77. end process;
  78.  
  79. END;
  80.  
  81.