VHDL Code:
  1.  
  2.  
  3.  
  4. library IEEE;
  5. use IEEE.STD_LOGIC_1164.ALL;
  6.  
  7. entity Decoder is
  8. port
  9. (
  10. Sel : in std_logic_vector(2 downto 0);
  11. y : out std_logic_vector(7 downto 0)
  12. );
  13. end entity Decoder;
  14.  
  15. architecture Behavioral of Decoder is
  16. begin
  17. y <= "00000001" when Sel="000" else
  18. "00000010" when Sel="001" else
  19. "00000100" when Sel="010" else
  20. "00001000" when Sel="011" else
  21. "00010000" when Sel="100" else
  22. "00100000" when Sel="101" else
  23. "01000000" when Sel="110" else
  24. "10000000" when Sel="111";
  25. end architecture Behavioral;
  26.  
  27. --VHDL Test Bench:
  28.  
  29. LIBRARY ieee;
  30. USE ieee.std_logic_1164.ALL;
  31.  
  32. ENTITY TestDecoder IS
  33. END TestDecoder;
  34.  
  35. ARCHITECTURE behavior OF TestDecoder IS
  36. -- Component Declaration for the Unit Under Test (UUT)
  37. COMPONENT Decoder
  38. PORT(
  39. Sel : IN std_logic_vector(2 downto 0);
  40. y : OUT std_logic_vector(7 downto 0)
  41. );
  42. END COMPONENT;
  43.  
  44. --Inputs
  45. signal Sel : std_logic_vector(2 downto 0) := (others => '0');
  46. --Outputs
  47. signal y : std_logic_vector(7 downto 0);
  48. -- No clocks detected in port list. Replace below with
  49. -- appropriate port name
  50. constant clock_period : time := 10 ns;
  51. BEGIN
  52. -- Instantiate the Unit Under Test (UUT)
  53. uut: Decoder PORT MAP (
  54. Sel => Sel,
  55. y => y
  56. );
  57.  
  58. -- Stimulus process
  59. stim_proc: process
  60. begin
  61.  
  62. wait for 10 ns;
  63.  
  64. sel <= "000";
  65. wait for clock_period*1;
  66. sel <= "001";
  67. wait for clock_period*1;
  68. sel <= "010";
  69. wait for clock_period*1;
  70. sel <= "011";
  71. wait for clock_period*1;
  72. sel <= "100";
  73. wait for clock_period*1;
  74. sel <= "101";
  75. wait for clock_period*1;
  76. sel <= "110";
  77. wait for clock_period*1;
  78. sel <= "111";
  79.  
  80. wait;
  81. end process;
  82. END;
  83.