VHDL Code:
  1.  
  2. library IEEE;
  3. use IEEE.STD_LOGIC_1164.ALL;
  4.  
  5. entity Multiplexer_VHDL is
  6. port
  7. (
  8. a, b, c, d, e, f, g, h : in std_logic;
  9. Sel : in std_logic_vector(2 downto 0);
  10.  
  11. Output : out std_logic
  12. );
  13. end entity Multiplexer_VHDL;
  14.  
  15. architecture Behavioral of Multiplexer_VHDL is
  16. begin
  17. process (a, b, c, d, e, f, g, h, Sel) is
  18. begin
  19. case Sel is
  20. when "000" => Output <= a;
  21. when "001" => Output <= b;
  22. when "010" => Output <= c;
  23. when "011" => Output <= d;
  24. when "100" => Output <= e;
  25. when "101" => Output <= f;
  26. when "110" => Output <= g;
  27. when others => Output <= h;
  28. end case;
  29. end process;
  30. end architecture Behavioral;
  31.  
  32. Test Bench for Multiplexer in VHDL:
  33.  
  34.  
  35. LIBRARY ieee;
  36. USE ieee.std_logic_1164.ALL;
  37.  
  38.  
  39. ENTITY TextMultiplexer IS
  40. END TextMultiplexer;
  41.  
  42. ARCHITECTURE behavior OF TextMultiplexer IS
  43.  
  44. -- Component Declaration for the Unit Under Test (UUT)
  45.  
  46. COMPONENT Multiplexer
  47. PORT(
  48. a : IN std_logic;
  49. b : IN std_logic;
  50. c : IN std_logic;
  51. d : IN std_logic;
  52. e : IN std_logic;
  53. f : IN std_logic;
  54. g : IN std_logic;
  55. h : IN std_logic;
  56. Sel : IN std_logic_vector(2 downto 0);
  57. Output : OUT std_logic
  58. );
  59. END COMPONENT;
  60.  
  61.  
  62. --Inputs
  63. signal a : std_logic := '0';
  64. signal b : std_logic := '0';
  65. signal c : std_logic := '0';
  66. signal d : std_logic := '0';
  67. signal e : std_logic := '0';
  68. signal f : std_logic := '0';
  69. signal g : std_logic := '0';
  70. signal h : std_logic := '0';
  71. signal Sel : std_logic_vector(2 downto 0) := (others => '0');
  72.  
  73. --Outputs
  74. signal Output : std_logic;
  75. -- No clocks detected in port list. Replace below with
  76. -- appropriate port name
  77.  
  78. constant clock_period : time := 10 ns;
  79.  
  80. BEGIN
  81.  
  82. -- Instantiate the Unit Under Test (UUT)
  83. uut: Multiplexer PORT MAP (
  84. a => a,
  85. b => b,
  86. c => c,
  87. d => d,
  88. e => e,
  89. f => f,
  90. g => g,
  91. h => h,
  92. Sel => Sel,
  93. Output => Output
  94. );
  95.  
  96.  
  97. -- Stimulus process
  98. stim_proc: process
  99. begin
  100. -- hold reset state for 100 ns.
  101. wait for 10 ns;
  102. a<='0';
  103. b<='1';
  104. c<='0';
  105. d<='1';
  106. e<='0';
  107. f<='1';
  108. g<='0';
  109. h<='1';
  110.  
  111. sel <= "000";
  112. wait for clock_period*1;
  113. sel <= "001";
  114. wait for clock_period*1;
  115. sel <= "010";
  116. wait for clock_period*1;
  117. sel <= "011";
  118. wait for clock_period*1;
  119. sel <= "100";
  120. wait for clock_period*1;
  121. sel <= "101";
  122. wait for clock_period*1;
  123. sel <= "110";
  124. wait for clock_period*1;
  125. sel <= "111";
  126. wait;
  127. end process;
  128.  
  129. END;
  130.  
  131.