VHDL Code:
  1.  
  2.  
  3. library IEEE;
  4. use IEEE.STD_LOGIC_1164.ALL;
  5. use ieee.numeric_std.all;
  6.  
  7. entity Accumulator is
  8. Port ( clk : in std_ulogic;
  9. inPort : in std_ulogic_vector(7 downto 0);
  10. outPort : out std_ulogic_vector(7 downto 0);
  11. enable : in std_ulogic);
  12. end Accumulator;
  13.  
  14. architecture Behavioral of Accumulator is
  15. signal sum : std_ulogic_vector(7 downto 0) := "00000000";
  16. begin
  17.  
  18. accum_process: process (clk, enable)
  19. begin
  20. if (rising_edge(clk) and enable = '1') then
  21. sum <= std_ulogic_vector((unsigned(inPort) + unsigned(sum)));
  22. outPort <= std_ulogic_vector((unsigned(inPort) + unsigned(sum)));
  23. end if;
  24. end process accum_process;
  25. end Behavioral;
  26.  
  27.  
  28. --VHDL Test-bench for Accumulator:
  29.  
  30. LIBRARY ieee;
  31. USE ieee.std_logic_1164.ALL;
  32. USE ieee.numeric_std.ALL;
  33.  
  34. ENTITY test_Accumulator IS
  35. END test_Accumulator;
  36. ARCHITECTURE behavior OF test_Accumulator IS
  37. COMPONENT accumulator
  38. PORT(
  39. clk : IN std_ulogic;
  40. inPort : IN std_ulogic_vector(7 downto 0);
  41. enable : IN std_ulogic;
  42. outPort : OUT std_ulogic_vector(7 downto 0)
  43. );
  44. END COMPONENT;
  45.  
  46. SIGNAL clk_wire : std_ulogic := '0';
  47. SIGNAL inPort : std_ulogic_vector(7 downto 0);
  48. SIGNAL outPort : std_ulogic_vector(7 downto 0);
  49. SIGNAL enable : std_ulogic;
  50. BEGIN
  51. uut: accumulator PORT MAP(
  52. clk => clk_wire,
  53. inPort => inPort,
  54. outPort => outPort,
  55. enable => enable
  56. );
  57. --Here we create our clock
  58. clk_wire <= not(clk_wire) after 10 ns; -- creating our clock with period 20ns
  59. tb : PROCESS
  60. BEGIN
  61. wait for 20 ns;
  62. enable <= '1';
  63. inPort <= "00000010";
  64. wait for 60 ns;
  65. inPort <= "00000100";
  66. wait for 40 ns;
  67. enable <= '0';
  68. wait for 60 ns;
  69. wait;
  70. END PROCESS;
  71.  
  72. END;
  73.  
  74.  
  75.