PRBS Generator:

Pseudo random binary sequence is essentially a random sequence of binary numbers. So PRBS generator is nothing but random binary number generator.  It is ‘random’ in a sense that the value of an element of the sequence is independent of the values of any of the other elements. It is 'pseudo' because it is deterministic and after N elements it starts to repeat itself, unlike real random sequences. The  implementation  of  PRBS  generator  is  based  on  the  linear  feedback  shift  register (LFSR). The PRBS generator produces a predefined sequence of 1's and 0's, with 1 and 0 occurring with the same probability. A sequence of consecutive n*(2^n -1) bits comprise one data pattern, and this pattern will repeat itself over time.

A PRBS generator is implemented in VHDL, using LFSRs.(Linear feedback Shift Registers which is made up of D-Flip-flops).Here is an example of How it can be done using VHDL.

```VHDL Code:library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dff is
Port ( CLK : in std_logic;
RSTn : in std_logic;
D : in std_logic;
Q : out std_logic);
end dff;

architecture Behavioral of dff is
begin
process(CLK)
begin
if CLK'event and CLK='1' then
if RSTn='1' then
Q <= '1';
else
Q <= D;
end if;
end if;
end process;
end Behavioral;

VHDL CODE FOR PRBS Generator using LFSR:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lfsr is
Port ( CLK : in  STD_LOGIC;
RSTn : in  STD_LOGIC;
data_out : out  STD_LOGIC_VECTOR (15 downto 0));
end lfsr;

architecture Behavioral of lfsr is

component dff
Port ( CLK : in std_logic;
RSTn : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;

signal data_reg : std_logic_vector(15 downto 0);
signal tap_data : std_logic;

begin
process(CLK)
begin
tap_data <= (data_reg(1) xor data_reg(2)) xor (data_reg(4) xor
data_reg(15));
end process;

stage0: dff
port map(CLK, RSTn, tap_data, data_reg(0));

g0:for i in 0 to 14 generate

stageN: dff
port map(CLK, RSTn, data_reg(i), data_reg(i+1));
end generate;
data_out <= data_reg after 3 ns;
end Behavioral;

VHDL Test Bench for Simulation:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY testprbs IS
END testprbs;

ARCHITECTURE behavior OF testprbs IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT lfsr
PORT(
CLK : IN  std_logic;
RSTn : IN  std_logic;
data_out : OUT  std_logic_vector(15 downto 0)
);
END COMPONENT;
signal CLK : std_logic := '0';
signal RSTn : std_logic := '0';
signal data_out : std_logic_vector(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: lfsr PORT MAP (
CLK => CLK,
RSTn => RSTn,
data_out => data_out
);
CLK_process :process

begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
wait for 10 ns;
wait for CLK_period*1;
RSTn <= '1';
wait for CLK_period*1;
RSTn <= '0';
wait;
end process;

END;

```